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Performance improvements

Improving performance means obtaining higher throughput, lower latency, and lower CPU load during communication. The communication performance depends on both network and interface performance. Network performance is influenced by the communication protocol, as discussed in Section 5. The interface performance is determined by the efficiency of the implementation of the required operations.

We can distinguish three classes of operations: (1) O(message length) operations, such as copying of message data and CRC checking, (2) O(nr of packets) operations, the handling of packets, and (3) O(nr of messages), communication initialisation and task switching.

By using DMA directly to process space and a reliable network, we have avoided implementing any O(message length) operations on the CPU. The maximum throughput is therefore limited by the C101 hardware and not by the CPU power. We have chosen to implement the O(nr of packets) operations, i.e., the packet handling, on an interrupt basis. The O(nr of messages) operations are implemented as kernel calls that execute reschedule operations.

We focus on two methods to improve performance: using the DSNIC board for packet handling, and using alternatives for OS functionality. By extending the Comms1 and 2 communication model so it takes the CPU load caused by communication into account, we can estimate the effect of the two performance improvements on the throughput and the CPU load graph, see Figure 12.

  
Figure 12: The effects of two performance improvement methods on the throughput and CPU load graph for Comms2 and packet size 1024. Graph A models the performance of the current system when using threads to perform the computation. Graph B models the performance of a system in which all packet handling is off-loaded to the DSNIC board. Graph C models the performance of a system with low-latency context switches. Graph D models a system that takes both the advantages of B and C. Compared to A and B, graphs C and D show an improvement in throughput.




next up previous
Next: Modelling the CPU load Up: A PCI based Previous: Interrupt overhead

Marcel Boosten
Wed Mar 11 14:25:07 MET 1998