The HS-Link Network Interface Card can provide two different functions: it can be used as a traffic generator for the network testbed and it can also provide an interface to the PCI bus to allow processor access to the HS-Link. The second feature can be used either for control purposes or using high speed DMA access for processor to processor, high speed, low latency data communications.
The block diagram of the network interface is shown in figure 7. A PCI interface chip provides for user DMA, mailboxes, interrupts and bus interfacing. Glue logic implemented in a FPGA handles the multiplexing of this interface between two HS-Link channels. Each channel handles a HS-Link Bullit interface. State machines to read or write the Bullit input and output FIFOs are implemented in the control FPGA. The HS-Link packets can be transferred to or from the PCI bus directly thus fulfilling the processor to processor communication requirements.
Figure 7: Block Diagram of the PCI HS-Link Interface
Each control FPGA has access to two memory banks. One for the transmitted data and one for the received data. To exercise the links at full bandwidth, data packet descriptors are stored in the transmit memory. These descriptors contains the packets destination address, its length and its required time of despatch. These variables are sufficient to fully define the traffic profile that will traverse the switching network.
State machines in the control FPGA interpret these descriptors and transmit the defined packet as requested. Packets are timestamped on reception, their delays calculated and the results stored in the reception memory which is regularly read out by a control processor across the PCI bus. Control software drivers have been developed for the Linux operating system. The prototype board is currently under test.